PPL Phase Lock Loop 4046

 

Stan Meyers PPL Phase Lock Loop 4046 with sample and hold network
Simple and basic schematic to see the workings of the 4046 PLL IC used in the Stanley Meyer circuits. See the forum thread 'Complete VIC schematic and pcb (work in progress)' on the RWGResearch forums for a pdf with the schematics of this simple test.

Matt can you share feedback circuit you use ,  that work the best on Coils ,please?

 

 

ndy, this is the circuit I plan on testing next once my parts get here.  I'll drive it with 5 volts like everything else.  I expect it to work the best, but still need to run it through the paces.

I'm currently using Stan's circuit with the LM741 replaced by a LM358.  It's okay, but not the best.  Not real stable either--I notice the behavior change when I attach a scope probe.

The thing to keep in mind is that whatever signal the feedback circuit produces, that's the signal the PLL will track, so it's important the feedback circuit sees the right thing.  Part of this is the pickup coil or sensor and the rest is the feedback circuit itself.  With the circuit below, it's probably best to use shielded coax from the pickup coil back to the feedback circuit, which can be done pretty easily since one side is grounded.

Thank you very much I will build this circuit.
Matt when scanning circuit change frequency of the PLL - then PLL seeks for max amplitude of signal and lock to this frequency of max amplitude ?

 

I'm not implementing the scanning circuit at this point.   From what I can see so far, the PLL does everything we need.  If the PLL is configured to have its capture range anywhere around the actual resonant frequency point, the PLL will find this frequency and track it automatically.  All that is needed is to adjust the PLL center frequency so that it's somewhere close to the actual resonant frequency of the VIC and WFC.  I'm currently looking at how to best adjust the capture range so the PLL doesn't attempt to lock on a harmonic, which can happen if the center frequency is set too high.

The PLL itself doesn't look at amplitude at all.  It finds the edge of the signal, typically at the zero crossing.  Hence, it's called a phase lock loop, because phase is what it is tracking.  The means it uses to do this is by adjusting its internal VCO frequency until the phase angles line up or match.  The output of the VCO drives the VIC and the feedback into the PLL phase detector determines how good a match it has and adjusts the frequency of the VCO accordingly.  What you get in the end is exactly like you said--maximum amplitude or a resonant condition with voltage and current exactly 90 degrees from each other.  This is the crux of impedance--a condition where at maximum voltage, there is zero current, which is why the voltage rises--there's nothing to stop it.  Resistance can "impede" current, but it cannot do anything to voltage.  So with no current, no resistance is felt by the tank circuit.  Keep in mind this is only true precisely where the current is zero; at any other phase angle this is no longer true--regular Ohm's Law rules apply.

Where I'm a little concerned about all this is the talk of frequency doubling.  What this is, is a wave traveling through the coils and bouncing back in such a way where you have two waves superimposed on each other--one came from the driver and the other is the reflected wave.  I suspect the feedback may see both of these waves; if it does, it will try to speed up the VCO to match the phase, which is not what we want.  I'm not real sure yet how Stan handled this unless by purely using a filter.  It should be possible to take the signal exiting the feedback circuit and divide this by two before sending it to the PLL phase detector.  I can't see that Stan did this or if he did, I'm not understanding how without using a D flip-flop or something similar.  Maybe based on where the pickup coil is positioned, the feedback circuit never sees the reflected wave.  Just not real certain at this point, but we will find out.

 

 

Thank You Matt very very much for this explanation which help me understand how pll work. It was big mystery for my.
thankyou

 

Matt
Is the pickup coil and resonant feedback circuit see the ringing of LC circuit on its natural frequency after pulse from the primary coil from output "4" of PLL? 

 

By way of the driver circuit yes, that's what should happen.

The VIC & WFC is the bell.  The pulse from the driver is the hammer that strikes the bell.  The pickup coil is the microphone and the feedback circuit is the amplifier.  What the PLL hears coming from the feedback circuit tells it exactly when to strike the bell with the hammer to get it ringing as loud and strong as is possible.

 

What is the task of signal going from primary coil thru 22k resistor and 330 pF cap to input "3" of PLL?

 

The only thing I can think of is this little low-pass filter network is what keeps the PLL focused on the fundamental frequency as I mentioned earlier.  Otherwise it is fully possible the PLL might try to lock on both the main and the reflected wave, forcing it to speed up.

What I find disconcerting is the way this bodge is connected.  The VCO Output (pin 4) is connected to the Comparator Input (pin 3) which is right where this filter terminates, so it's pushing against another output which is typically not a good thing to do.  I have no idea what kind of signal strength might try to get through that filter.  It has the potential of popping the CD4046 chip with a strong enough impulse.  The diode in parallel with the primary is a must-have component with the filter connected.

I've seen a lot of electronic circuits over the years that are not correctly designed, even though they appear to work properly.  This may be one of those quick-n-dirty solutions Stan used to avoid having new boards fabricated.  The three decade counters is also another clue Stan didn't really know for sure what to expect when he connected up the VIC card to his system.  If he would have known in advance exactly what frequency range to expect, he would have designed the VIC card to run at that range and no other.  Like us now, Stan's card was a work-in-progress.

 

Let's not forget Matt, some of the other ViC's went to other things like the gas processor steam resonator ect. which would require different ranges but could use the same card if it had different ranges to work with. It's all appreciated Ronnie.  The more we learn, the more we grow.

Yes, it does make sense that Stan would build multi-purpose boards.  I'm not quite at that level yet.  I like purpose-built things still.   :-)   Probably comes from being a software engineer for so many years.

=============================================

Boy ain't that the truth.  Equipment, parts and lots of time reading, studying, building and getting quite frustrated when things don't seem to come together.

So Ronnie, did you say crackling like bacon...?

I was playing around tonight with my circuit and noticed I couldn't run too long without a heatsink on my voltage control regulator, so I pulled it out and mounted a nice heavy copper heatsink to it.  After that, I cranked up the juice and decided to connect my wound bobbins and core (that I know won't work, but are good enough to tinker with) so I could see how the PLL, gating and feedback all work with real parts hooked to it.  I started at 2 volts and just slowly turned up the voltage watching the scope.  Everything except the feedback was working real good.  The feedback was all over the map causing the PLL to jump around constantly trying to lock onto the screwy signals.  What the heck, I figured I'd crank up the voltage some more and just see what happens, maybe the thing would settle down with a stronger signal.  That's not at all what it did though.  At about six volts the core was starting to hiss and squeal a little; by the time I got to ten volts the core was going nuts--popping, scratching, hissing like a pressure cooker about to blow.  The scope was just a blur of signals jumping all over the place.  It really made me think about "crackling like bacon".  If that kind of chaotic signal is what's needed to get the water to pop apart, it sure looks like this circuit can do it.  Hopefully it doesn't let too many demons out--they sure sound ticked off.

============================================

You should have signals jumping all over the place on the scope. From the sound of things you got it going on Matt.

 

Matt, do you have the cores fastened really well? 
what was on the coil side? cap diode or just the coil(s) ? 

i know when my cores are not hald really nice they want to chatter like crazy, but its not the same as " bakin" 

~Russ
=======================================

The feedback was all over the map causing the PLL to jump around constantly trying to lock onto the screwy signals.

this was my experience in the bast with the PLL and stans circuit. Tony wood sides, the one we made here, and soon to test a SM VIC card " replaca" type will see how it dose...

~Russ 

 

===============================

All I can say for the moment is we need to follow the clues wherever they lead.  Look at it all as though you were a child and assume nothing.

============================

There is a way to cancel out the pulsing circuit from the feedback. All you're left with are harmonics to lock onto. Try that.
Is this already designed in the circuit?

 

If one were to place a CSR at the cell, I suspect what you would see would be completely independent of the pulses going into the primary.  If that signal was properly isolated, amplified, squared off (clipped) and fed back to the PLL, I have no idea what might happen.  The problem I think we would have in doing that is isolation--20,000 volts is a lot to deal with, both signal-wise and power.

"The voltage can reach up to infinity, if the electronic components allow it to happen." ~Stan

  •  

Matt
You wrote:
Where I'm a little concerned about all this is the talk of frequency doubling.  What this is, is a wave traveling through the coils and bouncing back in such a way where you have two waves superimposed on each other--one came from the driver and the other is the reflected wave.  I suspect the feedback may see both of these waves; if it does, it will try to speed up the VCO to match the phase, which is not what we want.  I'm not real sure yet how Stan handled this unless by purely using a filter.  It should be possible to take the signal exiting the feedback circuit and divide this by two before sending it to the PLL phase detector.  I can't see that Stan did this or if he did, I'm not understanding how without using a D flip-flop or something similar.  Maybe based on where the pickup coil is positioned, the feedback circuit never sees the reflected wave.  Just not real certain at this point, but we will find out.
end quote

Matt maybe it is the ansver:
Stan used 741 chip , I find this:
741 IC is relatively slow which limits the usage of zero-crossing detectors with it to around 10 KHz.

Sorry Stan used ECG918M but I cant find its datasheet.
andy

 

The probable equivalent to ECG918M can be the LM318N fast opAmp and it is cheap. Can anyone confirm this?

 

=====================================================

 

Andy, we see 741 Op-amps in the estate photos and though they are typically used with bipolar power supplies, they were used nonetheless.  I'm pretty certain they will operate well into the ultrasonic frequency range.

On the issue of frequency doubling, here's a little video of a friend of mine in Whales that was able to replicate such a phenomena.  In this case he suspects the core halves were vibrating causing this effect to manifest.

 

Double the frequency through the split.

Take a look at where Stan put his pickup coil.

Slope Detector -- another variation for the feedback circuit.  Probably should try it and see how it behaves.

This should sync pretty well on the sine rise & fall times and pickup any harmonics that may be in the signal, unlike Stan's detector that will clip everything except the main signal.

Keep in mind the VCO never stops running.  All the gate signal does is blank the output going to the driver transistors.  During this time the PLL may begin to drift (towards baseline) if no feedback is seen from the core.  If feedback is still present (the core is ringing), then the PLL will remain locked on frequency.

With no feedback the amount if drift is determined by how long the feedback is suppressed.  Long intervals will cause the VCO to reset all the way back to the base frequency of 1kHz.  Short intervals will allow the VCO to drift somewhere in between the current running frequency and the base frequency.  The low-pass filter network connected to the PLL determines how responsive this drift is.

Quote from Gunther Rattay on March 10th, 09:23 AM

a % of last frequency would be good to know. the longer the gating the more derivation will be. time for adjustment will depend on bit bang capacitor.

You could take the Application Notes PDF for the 7046 and run the numbers to get a good estimate.  The components used on this board seem to be a reasonable starting point.  I suspect once we have a cell running and we know the center frequency, all the components could be adjusted slightly around this frequency.

 

 

 Though I may be in error according to the logic diagram.

It's hard to tell if the inhibit pin is actually stopping the VCO or not.  If it actually stops the VCO, then when the inhibit signal is lifted, the VCO "appears" to pick up at the exact point where it was stopped.  It's possible though the VCO instead begins a new cycle.  This would likely create some jitter in the output.

What I do know is with the additional logic around the gating and inhibit, the pulses stream presented to the driver transistors is always 50% duty cycle.  There are no chopped or partial pulses when the inhibit pin is activated or when it is restored to normal running.

 

 

Matt
Can you look on this:

Can you look on this:

In that logic diagram is sure looks like the inhibit stops the flip-flop.  So I would have to say when the inhibit is deactivated, the VCO starts a clean new cycle which may not be in-phase with the VCO output prior to the inhibit going active.  That would definitely create some jitter.

Question is:  Is that jitter harmful to the overall function?  Or more important, is it actually necessary, meaning the VIC needs this jitter to do what it does?  If it does, then the gating becomes rather critical to the overall operation.  Small changes in the delay and duration of the gating could make a huge difference in the behavior of the VIC.

 

Question is:  Is that jitter harmful to the overall function?  Or more important, is it actually necessary, meaning the VIC needs this jitter to do what it does?

By how much jitter (or latency or delay) does it become harmful?: 20 milliseconds, 100 milliseconds, 1 second? Is it harmful? Can it self-correct?Limits are defined. If there is high frequency jitter, in an event that it is determined harmful, you would need a low-pass filter there to define a limit.

Quote from Matt Watts on March 11th, 03:40 PM

If it does, then the gating becomes rather critical to the overall operation.  Small changes in the delay and duration of the gating could make a huge difference in the behavior of the VIC.

What is the intended "behavior"?You can hold a _stable_ PLL lock on a main carrier frequency, like a modern radio does, and still have jitter. If a limit is defined, "harmful" jitter would be mitigated.

 

============================

 

A few cycles of jitter is nothing.

Jitter as long as 1 or 10 Hz is concerning. As well as 100 kHz of jitter.

A limit, or bandwidth, is defined.

 

===============

 

Matt
When you gate the PLL can you zoom-in on the o-scope a few first cycles after gating is disabled , please?

 

==================

The PLL should recover after an inhibit. I'm not sure what its behavior is after a few cycles looks like.

 

==================

When you gate the PLL can you zoom-in on the o-scope a few first cycles after gating is disabled , please?

The gate logic that is preventing partial pulses is working properly.  Really hard to tell about jitter unless you are accurately tracking the phase angle.

Here's a couple of scope shots.  The first one would indicate to me the VCO is resetting; the second one ...?   Can't say.

This is running with actual core feedback, so it's a little dicey.

It certainly would be possible to re-arrange the logic a little to prevent the VCO from halting and restarting.  Whether this would be a worthwhile endeavor is hard to say.

 

 

he top trace is feedback from the core? Frequency top v. bottom trace?

  • MattWhere was connected the probe of o-scope at?Thank

    Where was connected the probe of o-scope at?

    Directly across VIC primary.  Signal is much cleaner upstream of driver transistors.

=====================

he top trace is feedback from the core? Frequency top v. bottom trace?

Just a snapshot zoomed, centered on the gating.  Looking at two consecutive gate signals.

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